I. Field of the Disclosure
The technology of the disclosure relates generally to magnetic tunnel junctions (MTJs) used to provide memory cells.
II. Background
The electronics industry commonly uses switches as a component of circuit design. To date, these switches have been charge based switches, such as a CMOS or MOSFET switch. Power consumption in such charge based switches remains a concern and there remains continued pressure to find low power alternatives to existing switching technology.
Magnetic tunnel junctions (MTJs) can be used as switches, but are more frequently used in memory applications, such as magnetic random access memory (MRAM), which is non-volatile memory in which data is stored by programming an MTJ. However, conventional MTJs consume certain amounts of power in switching between states. In many devices, such as portable electronics, there is a general goal to reduce power consumption by such memory elements.
Despite the power consumption of an MTJ, MRAM is advantageous because the MTJ can be used to store information even when power is turned off. Data is stored in the MTJ as a small magnetic element, rather than an electric charge or current. An exemplary MTJ 10 is illustrated in FIG. 1. Data is stored in the MTJ 10 according to the magnetic orientation between two layers: a free layer 12 disposed above a fixed or pinned layer 14. The free and pinned layers 12, 14 are formed from a ferromagnetic material. The MTJ 10 is configured in a conventional “bottom-spin valve” configuration wherein the pinned layer 14 is disposed below the free layer 12. The free and pinned layers 12, 14 are separated by a tunnel junction or barrier 16 formed by a thin non-magnetic dielectric layer. The free and pinned layers 12, 14 can store information even when the magnetic H-field is ‘0’ due to the hysteresis loop 18 of the MTJ 10. Electrons can tunnel through the tunnel barrier 16 if a bias voltage is applied between two electrodes 20, 22 coupled on ends of the MTJ 10. The tunneling current depends on the relative orientation of the free and pinned layers 12, 14. When using a spin-torque-transfer (STT) MTJ, the difference in the tunneling current as the spin alignment of the free and pinned layers 12, 14 is switched between parallel (P) and anti-parallel (AP) is known as the tunnel magnetoresistance ratio (TMR).
When the magnetic orientations of the free and pinned layers 12, 14 are anti-parallel to each other (shown in FIG. 1 as MTJ 10′), a first memory state exists (e.g., a logical ‘1’). When the magnetic orientations of the free and pinned layers 12, 14 are parallel to each other (shown in FIG. 1 as MTJ 10″), a second memory state exists (e.g., a logical ‘0’). The magnetic orientation of the free and pinned layers 12, 14 can be sensed to read data stored in the MTJ 10 by sensing the resistance when current flows through the MTJ 10. Data can also be written and stored in the MTJ 10 by applying a magnetic field to change the orientation of a free ferromagnetic layer 12 to either a P or AP magnetic orientation with respect to the pinned layer 14. The magnetic orientation of the free layer 12 can be changed, but the magnetic orientation of the pinned layer 14 is fixed.
FIG. 2 illustrates an STT MU 23 (referred to as “MTJ 23”) of similar design to the MTJ 10 in FIG. 1. The MTJ 23 is provided as part of an MRAM bitcell 24 to store non-volatile data. The MRAM bitcell 24 may be provided in a memory array and used as memory storage for any type of system requiring electronic memory, such as a computer processing unit (CPU) or processor-based system, as examples. A metal-oxide semiconductor (typically n-type MOS, i.e., NMOS) access transistor 26 is provided to control reading and writing to the MTJ 23. The drain (D) of the access transistor 26 is coupled to the bottom electrode 22 of the MTJ 23, coupled to the pinned layer 14. A word line (VWL) is coupled to the gate (G) of the access transistor 26. The source (S) of the access transistor 26 is coupled to a voltage source (VS). A bit line (VBL) is coupled to the top electrode 20 of the MTJ 23, which is coupled to the free layer 12.
When reading data stored in the MTJ 23, the word line (VWL) is activated for the access transistor 26 to allow a small current to flow through the MTJ 23 between the electrodes 20, 22. A low resistance, as measured by voltage applied on the bit line (VBL) divided by the measured current, is associated with a P orientation between the free and pinned layers 12, 14. A higher resistance is associated with an AP orientation between the free and pinned layers 12, 14. When writing data to the MTJ 23, the gate (G) of the access transistor 26 is activated by activating the word line (VWL). A voltage differential between the bit line (VBL) and the source line (VS) is applied. As a result, a write current (I) is generated between the drain (D) and the source (S). If the magnetic orientation is to be changed from AP to P, a write current (IAP-P) flowing from the top electrode 20 to the bottom electrode 22 is generated, which induces a STT at the free layer 12 to change the magnetic orientation of the free layer 12 to P with respect to the pinned layer 14. If the magnetic orientation is to be changed from P to AP, a current (IP-AP) flowing from the bottom electrode 22 to the top electrode 20 is produced, which induces an STT at the free layer 12 to change the magnetic orientation of the free layer 12 to AP with respect to the pinned layer 14.
Regardless of whether the device is provided as a switch or a read/write memory device or to what state the device is changing, a certain amount of current (i.e., power) is required. Power consumption shortens battery life in mobile terminals such as mobile phones and generates waste heat which must be dissipated in all devices. Thus, as noted above, there is a generally desired goal to reduce power consumption in processor based systems that may employ MRAM.